Circuits for the distribution and synchronization of timing information play a key role in a number of applications which require a synchronous transfer of data, such as networks for transferring telephone calls over various networks, including the internet, and the like.
Current methods of signal synchronization between sub-networks do not provide complete synchronization. Incomplete synchronization results in data losses called slips. Compensating networks, including buffer circuitry, are typically used to compensate for slips caused by a lack of clock synchronization.
Those having skill in the art will understand the desirability of having a completely synchronous timing of sample collection and reconstruction that eliminates slips and the need for compensating circuitry. This type of network would provide complete synchronization of clocks between sub-networks by providing a series of clocks slaved to a master clock.